RISC-V VLSI Workshop: CISC vs RISC, RTL-to-GDS, FPGA Debug & Real Silicon Testing

VLSI System Design (VSD)

A workshop session from VLSI System Design (VSD) on RISC-V VLSI Workshop: CISC vs RISC, RTL-to-GDS, FPGA Debug & Real Silicon Testing. Best once you are comfortable with the basics of VLSI & Semiconductors. It plays here in the portal, and your progress is saved as you watch.